The present invention relates to a MOS semiconductor device, such as a MOSFET, for power and conductivity modulation-type MOSFETs (hereinafter designated as insulation gate bipolar transistors, or IGBTs) in which a U-shaped recess is formed in the semiconductor substrate so that the MOSFET channel is vertically oriented to the substrate surface.
In power MOSFETs and IGBTs, in conventional vertical power elements in which the main current runs vertically to the substrate, researchers have in the past tried to heighten the integrity density to reduce the element resistance while the device is in the ON state.
One way of doing this is to form a V-shaped recess on the substrate surface. But since the area utilization rate cannot be increased because of the V-shaped construction of the gate cut, U-shaped structures, as in Japanese Patents 1982-35591 and 1988-8624, have been proposed.
FIG. 2 shows a sectional view of a vertical MOSFET for power having a U-shaped structure. A U-shaped recess 4 of width A and depth B is formed from the surface on the P-base layer 3 of the silicon substrate having an N+ drain layer 2 and a P-base layer 3 with an N-layer 1 of low impurity concentration placed in between. On the surface of the P-base layer 3, an N+ source layer contacts the recess 4, and a polycrystalline silicon gate 7 is placed inside through an insulation film 6. A source electrode 8 contacts the P-base layer 3 and the source layer 5 which are not coated with an insulation film 5, and a drain electrode 9 contacts the N+ drain layer 2. In the element of this structure, an N-channel is formed between the source layer 5 of the P-base layer 3 which contacts the side wall of the recess 4 and the N-layer 1 by applying a voltage to the gate 7 to allow current flow. Since in this structure the channel is formed on the surface of the recess's side wall, it provides a higher area utilization rate for main current flow.
The thickness of the P-base layer 3 shown in FIG. 2 is approximately about 1-2 .mu.m in the case of power MOSFETs. In IGBTs, however, the layer is thicker, sometimes as much as 3-8 .mu.m.
Accordingly, the U-shaped recess 4 should be deep, and must be approximately 3-8 .mu.m. Wafer processing becomes difficult at such depths, however. With deep channels it is difficult to obtain uniform photo resist coatings and to match the photo-process mask, which deteriorates matching accuracy.
As shown in FIG. 2, one solution is to use polycrystalline silicon as a filler to make the surface even. Techniques for achieving evenness are well known in the field of LSI processing. Such techniques are used to fill memory cells in trenches with polycrystalline silicon, and to prevent cuts in electrode wiring made when the steps are formed. An example of this technology is shown in FIG. 3. In this method, a recess 32 in a substrate 31 is filled with polycrystalline silicon 33, then excess silicon is cut off to obtain an even surface. The recess 32 of width A and depth B, as shown in FIG. 3(a), filled with polycrystalline silicon 33 applied to a thickness over half the length of the width A. After filling the recess, etching is performed over the entire surface to obtain a flat configuration, as shown in FIG. 3(c). With this method, polycrystalline silicon approximately 1 .mu.m thick is enough for memory cells in trenches, where A is approximately 1 .mu.m and B is approximately 4 .mu.m. But in power MOSFETs and IGBTs like those shown in FIG. 2, A is as wide as 10-20 .mu.m of polycrystalline silicon. Another way to obtain even surfaces is by the steps shown in FIG. 3(b). In this method, polycrystalline silicon 33 is applied to a thickness greater than depth B. After coating resist, liquid glass, or the like is used to smooth the irregular surface of the polycrystalline silicon, uniform etching is performed over the entire surface to finally make the surface even. Even with this method, it is difficult to apply polycrystalline silicon to a thickness of 3-8 .mu.m when B is 3-8 .mu.m.
The object of this invention is to provide MOS semiconductor device in which surface evenness of the recess filled with polycrystalline silicon is easily achieved.